1. Field of the Invention
The present invention relates to a multilayer wiring structure of a multilayer wiring board (a multilayer circuit board for a multi-chip module) on which a plurality of semiconductor elements are to be mounted.
2. Description of the Related Art
FIG. 1 is an exploded perspective view of a multilayer wiring board for use in a conventional semiconductor device having a multilayer wiring structure. As shown in FIG. 1, the board comprises signal wiring layers S1 and S2, a power supply layer 31-1, and a ground layer 31-2. The signal wiring layers S1 and S2 are provided between the power supply layer 31-1 and the ground layer 31-2. The layers S1, S2, 31-1 and 31-2 are isolated from each other by insulating layers 20 (not shown). Each signal wiring layer comprises an insulator 32 and signal wires SP provided on the insulator 32. The power supply layer 31-1 comprises an insulator 32 and a mesh power-supply conductor pattern VP provided on the insulator 32. The ground layer 31-2 comprises an insulator 32 and a mesh ground conductor pattern GP.
FIG. 2 is a plan view showing the mesh ground conductor pattern GP9 and the signal wires SP9 of the signal wiring layer S2 as viewed in a direction A shown in FIG. 1. The signal wires SP9 are arranged in parallel with each other and extend parallel to the column lines of the ground conductor pattern GP9 and perpendicular to the row lines thereof. The signal wires SP9 of the power supply layer 31-1 have the same positional relationship with the conductor pattern VP of the signal wiring layer S1, when viewed in a direction B shown in FIG. 1.
FIGS. 3 to 5 are plan views showing other pattern structures. The pattern structure shown in FIG. 3 has signal wires SP10 (only one shown) which extend at 45.degree. to the column and row lines of the ground pattern GP10. The pattern structure shown in FIG. 4 has a ground conductor pattern GP11 having far less column lines than row lines, and wires SP11 (only one shown) extend parallel to the column lines of the pattern GP11. The pattern structure shown in FIG. 5 has a plane ground conductor pattern GP12, and wires SP12 (only one shown) extend parallel to one side of the conductor GP12.
Both line capacitance and line inductance are important design items of a signal wiring structure suitable for high-speed signal propagation. This is because a signal-propagation delay constant Tpd is given as: EQU Tpd=.sqroot.(L.multidot.C) (1)
where L is line inductance per unit length and C is line capacitance per unit length.
The greater the line capacitance C, the greater the overlapping area of the conductor and the wire, if the insulating layers provided between the conductor patterns and the wiring patterns have the same thickness, and are made of the same material. Of the structures shown in FIGS. 2 to 5, the structure shown in FIG. 5 has the largest capacitance C, the structure shown in FIG. 4 the smallest capacitance C, and each of the structures 2 and 3 has intermediate capacitance C.
The line inductance L can be expressed as: EQU L=Ls+Lg-2M=Ls+Lg-2k .sqroot.(Ls.multidot.Lg) (2)
(k=coupling coefficient) PA1 a potential supply layer including a plurality of parallel strip-shaped conductors each of which has a predetermined potential; and PA1 a signal wiring layer which includes a signal wires arranged in parallel with the conductors of the potential supply layer, and which is provided on the potential supply layer, with an insulating layer interposed between the potential supply layer and the signal wiring layer.
where is Ls is self-inductance of the signal wire SP, Lg is self-inductance of the conductor pattern GP of the ground layer, and M is mutual inductance of the signal wire SP and the conductor pattern GP.
As shown in FIG. 6, when a signal current SI flows in the signal wire SP, a current GI (a return current) flows in the conductor pattern GP in the opposite direction. The current GI increases the mutual inductance of the signal wire SP and the ground pattern GP. As a result, the line inductance increases. Therefore, the mutual inductance increases to a maximum, if the conductor completely overlaps with the wire in parallel therewith. If the conductor extends perpendicular to the wire, the mutual inductance decreases to almost nil.
In the multilayer wiring structure, the mutual inductance is an important factor reducing the line inductance. For example, of the structures of FIGS. 2 to 5, the structure of FIG. 5 has the largest mutual inductance M, the structure of FIG. 4 the smallest inductance M, and each of the structures of FIGS. 2 and 3 intermediate inductance M. Thus, the line inductance L of the structure of FIG. 4 is the largest, that of the structure of FIG. 5 the smallest, and that of each of the structures of FIGS. 2 and 3 intermediate.
As may be understood from the above, in the parameter design of the wiring structure, the line inductance L, as well as the line capacitance C, is important in the above equation (1).
In the structures of FIGS. 2 to 4, the line capacitance decreases, but the line inductance considerably increases, since it is not decreased by the mutual inductance. This is because a power supply/ground current hardly flow in the direction opposite to the signal current. Thus, the structures of FIGS. 2 to 4 increase the line inductance, and also the signal propagation delay time as the equation (1) indicates. Obviously, those structures are not suitable for high-speed signal propagation. In other words, a structure needs to reduce the line inductance if used to achieve high-speed signal propagation. It is preferable that the power supply/ground layer have a plane conductor like the conductor pattern of the power supply/ground layer of FIG. 5.
However, with the multilayer wiring structure, it is necessary to discharge gas or moisture from the insulating layer to the outside during formation of the insulating layer, if the insulating layer is formed of resin material such as polyimide. To discharge the gas or moisture easily, the power supply/ground layer needs to have a mesh conductor pattern. Such a power supply/ground layer, as explained above, is inferior to the power supply/ground layer having a plane conductor pattern in terms of the electrical characteristic. For example, in the power supply/ground layer having the mesh conductor pattern, the propagation delay time increases or a signal wave is distorted.
Very few analyses have been made of the electrical characteristics of the mesh patterns. To design the mesh conductor pattern, a TEM wave approximation method is generally used, for determining the line capacitance of the signal wire and the power supply/ground layer. In other words, the TEM wave approximation method does not involve the line inductance. However, to design a signal wiring layer suitable for high-speed signal propagation, the line inductance, as well as the line capacitance, must be considered, as is clear from the above explanation and the above equation (1).
Thus, in the mesh conductor pattern formed according to the TEM wave approximation method, the line inductance may increase. Therefore, in designation of the conductor pattern, it should be noted that a conductor pattern for optimizing the line capacitance is not necessarily the same as a conductor pattern for optimizing the line inductance.